This invention is related to the electronic design of very large scale integrated circuits (VLSI), and more particularly to a static timing analysis that guarantees the functionality and performance of a VLSI chip.
Conventional static timing analysis normally assumes static loads and nets. Coupling in the form of interaction between adjacent wires causes disturbances that are not easily handled by a conventional static timing analysis. One reason is that coupling can prevent levelization of the logic network upon which static timing analysis algorithms depend.
Coupling capacitance occurs when two neighboring wires are in close proximity of each other. Depending on how the signals rise or fall on these wires, delay and slew change on the victim net (defined as the net whose switching is affected). Slew is the time it takes for a signal transition to occur, e.g., to rise from 10% of the supply voltage to 90% of the supply voltage. Referring to FIG. 1, the aggressor nets (defined as the nets whose switching affects the victim's delay) or neighboring nets, undergo an opposite transition than the victim net. Consequently, the delay and transition time of the victim net increases. As seen in FIG. 2, aggressor nets may also undergo a transition in the same direction as the victim. Consequently, the delay and transition time in the victim net may decrease. These changes in delay and slew can be significant, and properly accounting for them becomes a significant problem.
Calculating the magnitude of the impact of capacitive coupling on the delay and slew depends upon several factors, including (a) the amount of capacitance; (b) the switching windows of the victim and aggressor nets, i.e., the range of times during which the nets make a transition; (c) the transition times (slews) of the victim and aggressor nets; and (d) the voltage swings of the victim and aggressor. From the information of (b), (c), and (d), a K-factor is calculated. The K factor represents the amount by which the effect of the coupling capacitance on the net increases or decreases as a result of switching occurring on the net to which it is coupled. The K-factor is multiplied by the capacitance to increase the victim capacitance (causing an increase in delay and slew), or to decrease the victim capacitance (causing a decrease in delay and slew).
The basic K-factor is described in U.S. Pat. No. 6,615,395 to Hathaway et al., although the values of K referenced herein do not coincide with the K factor Kprior used in the aforementioned patent, they rather correspond to 1−Kprior and 1+Kprior. Therefore, the term Kprior will preferably be used hereinafter to relate the current invention to this prior art.
The K-factor computation described in U.S. Pat. No. 6,615,395 is an iterative process. Initially, it starts with an assumption of worst-case K-factors when performing a timing analysis. In the first iteration, the worst-case timing is used to calculate the switching windows and determine new K-factors. The new K-factors are passed on to a timer, and a timing analysis is performed once again. In the second iteration, the updated timing results are used to calculate new switching windows, and thus new K-factors. Again, the new K-factors are transferred to the timer and the timing analysis is once again performed. This process continues until convergence is achieved, following a criterion determined by the user.
Optimization engines typically perform trial design changes, and call upon a timing analyzer to incrementally update the timing information to decide whether or not the change improves the design. A method of incremental timing analysis is described in U.S. Pat. No. 5,508,937 to Abato et al. Current solutions perform these operations without including the effects of the capacitive coupling on the timing. The solution outlined previously does not lend itself to incremental changes because the victim paths depend on the timing information of their aggressor paths. This dependence will now be explained.
Referring to FIG. 3, two neighboring paths of logic, a victim path, and an aggressor path are shown. Assume that an iterative timing analysis has already been performed and that the ‘K-factors’ have already been calculated for each coupling capacitance in the design. A change in net 4, for instance, affects the timing downstream to that change (i.e., nets 5 and 6). In addition, since the timing of net 4 is changing, its switching window (i.e., the range wherein a transition takes place) will change, and the timing impact of coupling on any nets for which the changed nets are aggressors must be re-analyzed. More specifically, a change in timing in net 4 implies that the K-factors may change between net 1 and net 4, between net 2 and net 5, between net 3 and net 6, and so on. In turn, when nets 1, 2, and 3 are re-analyzed as a result of the change in timing in nets 4, 5, and 6, the nets 1, 2, and 3 to which they are coupled must also be re-analyzed, leading to a repeated analysis throughout the design.
In summary, present design automated optimization tools typically rely on incremental timing to quickly assess changes. Because capacitive coupling is becoming more significant in current and future integrated circuit technologies, designers need optimizers that are aware of the coupling impact on the timing. Since no method is known to exist that is capable of performing incremental coupling-impact-on-timing analysis without iterating over the entire design (causing a large runtime impact), the optimizer does not recognize the impact of its change on the coupled timing, and one is misled into thinking that a change is advantageous.
Without the ability to update timing, including the coupling impact on the timing in a fast incremental manner, run times for coupling-aware timing analysis have become far too cumbersome for use in optimization tools. The closer the optimizer approaches the accuracy of signoff timing analysis (i.e., the timing analysis used to determine whether the final design will satisfy all timing requirements), the less likely it will be that timing problems will be detected during signoff timing analysis, significantly reducing the design turn around time (TAT).